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    焊線封裝技術

    焊線封裝技術

    Wire bonding forms an interconnection between a chip to a substrate, substrate  to substrate, or substrate to a package. Wire bonding is generally considered the most cost-effective and flexible interconnect technology, and is used to assemble the vast majority of semiconductor packages today.


    Wire Bond interconnection is available in a number of packaging approaches at JCET:

    Copper Wirebond

    A lower cost alternative to gold, copper wire is becoming the material of choice for interconnection in wirebond packages. Copper wire provides similar electrical characteristics and performance to gold wire with lower resistivity, which can be a benefit where lower bond wire resistance is needed for device performance. JCET is ready to engage on wirebond package types with a Best Value BOM for each package to enable the most cost-effective copper wirebond solution.

    Laminate Packages

    Laminate-based Ball Grid Array interconnect technology(BGA) was first introduce as a solution to the increasingly high lead counts required for advanced semiconductors. BGA technology features leads on the bottom surface of the package in the form of small bumps or solder balls, and provides low inductance, ease of surface mounting, relatively low cost, and excellent package reliability. JCET offers a full suite of laminate-based BGA packages, including fine pitch, extremely thin, multi-die, stacked and thermally enhanced configurations.

    In addition to standard laminate packages, JCET offers a broad portfolio of advanced stacked package options including a range of Package-on-Package(PoP) and Package-in-Package(PiP) configurations.

    Leadframe Packages

    Leaded packages are characterized by a die encapsulated in a plastic mold compound with metal leas surrounding the perimeter of the package. this simple and low-cost packaging is still the best solution for many applications. JCET provides a comprehensive range of leadframe package solutions from standard leadframe packages to low profile, small and thin, thermally enhanced packages, including Quad Flat Package(QFP), Quad/Dual Flat No-lead package(QFN/DFN) and Thin Small Outline Packages(TSOP), Small Outline Transistors(SOT), Small Outline Packages (SOP), Dual Inline Packages (DIP), Transistor Outline (TO).

    Memory Devices

    JCET offers memory card packaging in two formats, Micro-SD and SD-USB, in addition to value-added package assembly and test services. the Micro-SD is an integrated solution using NAND and controller die, while the SD-USB is a bare die, pre-packaged die with SMT components. JCET's memory card solution utilize bare die level assembly, pre-packaged die assembly or a combination of both.

    Full Service Packaging Design

    We collaborate with customers on die and package designs to provide the best possible products in terms of performance, quality, cycle time and cost. JCET's full-service package Design Centers help customers determine the optimum package for complex integrated circuits, and can assist customers in designing the most appropriate package for their specific device.

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    版權所有@江蘇長電科技股份有限公司 保留一切權利 蘇ICP備05082751號32028102000607

    版權所有@江蘇長電科技股份有限公司
    保留一切權利
    蘇ICP備05082751號 32028102000607
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