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    Characterization Services

    As the electronics industry moves towards more complex semiconductor packages that are smaller, faster and higher performance, engineers are faced with the challenge of trying to fit more powerful components into a smaller area without causing long term reliability issues or stress on a package.  Delivering the optimum package design requires an in-depth analysis of key package measurements and simulation.

    JCET offers the following characterization services:

    JCET’s worldwide package characterization teams located in China, Singapore, South Korea, and the United States provide advanced package characterization services for our global customers to ensure they have high quality, high performance, reliable and cost effective package designs that meet their market requirements. 

    Full-Service Packaging Design Centers

    JCET collaborates with customers on die and package designs to provide the best possible products in terms of performance, quality, cycle time and cost. JCET’s full-service package Design Centers help customers determine the optimum package for their specific end product.   

    Design Center services include: 

    ? Customer-centric designers 
    Mobile design capability 
    ? State-of-the-art design tools 

    ? Integration of customer supplied designs into JCET’s design system 

    ? Project data management 

    Proven Experience

    JCET’s world class design team has extensive experienced in the mobile, networking, computing, consumer and automotive markets. Their experience covers a wide range of Laminate, leadframe and wafer level package designs, including single die, multi-die, Package-on-Package (PoP), Integrated Passive Devices (IPD) and advanced System-in-Package (SiP). JCET’s dedicated design team has the necessary experience to provide complex designs that meet or exceed assembly and cost targets.

    Design for Performance

    Today's package designs adhere to stringent thermal and electrical requirements while providing high-end performance for our customers’ end products. To ensure a semiconductor package meet performance requirements, JCET’s Design and Characterization Team works closely with the customer through co-design while the integrated circuit (IC) is in development. The “Co-Design” of a package provides the best environment for optimum performance. JCET’s package designs meet our customers’ needs whether as a single chip device or complex System-in-Package (SiP).   

    The Design Process

    JCET manages the design process using our Product Data Management system. From the moment a request enters our system the design team works with our characterization experts and our customers to understand their needs for each design. As each new design is received, it undergoes a feasibility to determine if the package will meet the requirements of our factories, suppliers and customers. Our designers collaborate with customers to ensure the optimum package is produced with consideration to cost, assembly and function. 

    Design Tool Sets

    ? Cadence: SiP and APD 
    ? AutoDesk: AutoCad 
    ? Downstream: CAM350 
    ? Internally developed support tools
    聯系我們 |  客戶查詢 |  法律聲明

    聯系我們 客戶查詢 法律聲明

    版權所有@江蘇長電科技股份有限公司 保留一切權利 蘇ICP備05082751號32028102000607

    蘇ICP備05082751號 32028102000607
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