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    En

    晶圓凸塊

    晶圓凸塊

    Wafer Bumping

    Wafer bumping technology can provide significant performance, form factor and cost advantages in a semiconductor package. Wafer bumping is an advanced manufacturing process whereby metal solder balls or bumps are formed on the semiconductor wafer prior to dicing. Wafer bumps provide an interconnection between the die and a substrate or printed circuit board in a device. Solder bump composition and dimension depends on a number of factors such as form factor, cost and the electrical, mechanical and thermal performance requirements of the semiconductor device. 

    JCET is experienced in a wide range of wafer bump alloys and processes, including printed bump, ball drop and plated technology with eutectic, lead free and copper pillar alloys. Our wafer bumping offering includes wafer bump and redistribution for 200mm and 300mm wafer sizes for full turnkey advanced flip chip and wafer level packaging solutions.

    Flip Chip Packaging

    In flip chip packaging, the silicon die is directly attached to the substrate using solder bumps instead of wire bonds, providing a dense interconnection with a much higher bandwidth, faster data rates and increased electrical and thermal performance. The solder bumps and/or copper pillar bumps are placed on the active side of the device in a grid array pattern, either directly on I/O pads or routed from them. The most efficient implementation of flip chip technology occurs when the bump sits directly over the electronic cells to which they are connected (bump on I/O). The flip chip process employs the use of capillary underfill material (CUF) or molded underfill material (MUF) in the open spaces around the bumps and in the gap between the surface of the die and the circuit board to produce a highly reliable and stable structure. Flip chip interconnection is a key technology for a range of applications in the consumer, networking, computing, mobile and automotive markets.

    Wafer Level Packaging

    Wafer level packages (WLP) provide higher performance, functionality and speeds in a small, thin, lightweight device. Wafer level packages are similar to flip chip in that they utilize advanced wafer bumps as the interconnection to circuit boards. Whereas flip chip interconnection typically uses smaller solder bumps, wafer level packages utilize larger solder bumps with no underfill.  Many WLPs employ repassivation as a stress buffer layer for the circuitry beneath the bump. There are many variables to use in optimizing the design of a WLP, depending upon the cost-performance requirements. Wafer Level Packaging is a successful solution for established markets for mobile and handheld devices as well as emerging markets such as the Internet of Things (IoT), wearable devices and automotive electronics.

    Re-Passivation and Redistribution Layer (RDL)

    When additional die protection or additional structural support is required at the bump location, a single layer of polymer and metal is applied to the wafer. This process is referred to as re-passivation (RPV) since the addition of the polymer layer creates a second layer of passivation on the surface of the die. Repassivation is also used when the final metal bond pad is smaller than the diameter of the solder ball or under bump metallurgy (UBM) structure. The additional layer of dielectric material serves as a stress buffer layer, a planarizing medium and a finalpassivation layer to buffer the circuitry beneath the bump. 

    In situations where a device may have to function in both a wire-bondable peripheral pad arrangement or as a Flip Chip or Wafer Level component, an additional layer of lateral connections may be employed to reroute the input/output (I/O) layout into a completely new footprint.  This additional layer is known as a Redistribution Layer or RDL and may be fabricated from a thin layer of aluminum (Al), copper (Cu) or a combination of aluminum and copper (AlCu). Re-passivation and RDL are key enabling technologies for advanced fan-out wafer level technology such as embedded Wafer Level Ball Grid Array (eWLB), fan-in Wafer Level Chip Scale Packaging (WLCSP), Integrated Passive Devices (IPD), and System-in-Package (SiP) solutions.
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    版權所有@江蘇長電科技股份有限公司 保留一切權利 蘇ICP備05082751號32028102000607

    版權所有@江蘇長電科技股份有限公司
    保留一切權利
    蘇ICP備05082751號 32028102000607
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